Power generation utilizing natural energy such as sunlight or wind power is generally susceptible to environmental influence, and the amount of power generation fluctuates greatly. A system stabilizing device is used for the purpose of accommodating or absorbing this fluctuation.
In a microgrid having a network constructed by installing a power source, such as natural energy, near the electric power demand side, the installation of a system stabilizing device, which keeps demand for and supply of electric power in balance, is necessary for system stabilization.
An example of the microgrid (electric distribution or distribution system) equipped with a system stabilizing device will be described by reference to FIG. 7. FIG. 7 shows an example in which an existing superior power system (superior distribution system) 1 and a distribution system (microgrid) 10 are connected via a line impedance Ls and a circuit breaker 2.
A dispersed generation plant 11 and a load 12 are connected to the distribution system 10 which is the microgrid. The dispersed generation plant 11 is illustrated as a single generator in FIG. 7. Actually, however, it is composed of a plurality of dispersed facilities for power generation, which include natural energy type power generation equipment utilizing natural energy (e.g., photovoltaic power generation equipment or wind power generation equipment), and internal combustion engine type power generation equipment driven by an internal combustion engine (e.g., diesel power generation equipment). Also, the load 12 is actually a plurality of dispersed loads.
With the microgrid 10 as shown in FIG. 7, the amount of power generation varies or fluctuates greatly according to weather conditions, wind speed, etc., because it has natural energy type power generation equipment.
In order to accommodate such fluctuations in the amount of power generation, therefore, a system stabilizing device 20 is used.
With the internal combustion engine type power generation equipment, output power is adjusted by governor control. However, governor control is slow in response. Thus, if electric power consumed by the load 12 suddenly changes, the internal combustion engine type power generation equipment cannot follow such a sudden change (sudden excess or deficiency) in electric power. The system stabilizing device 20 is used for the purpose of following such a sudden change in electric power with good response, thereby assisting the internal combustion engine type power generation equipment to balance demand for and supply of electric power.
The system stabilizing device 20 is a power converter having a power storage function, and is provided in the distribution system 10 in a state connected in parallel with the dispersed generation plant 11 and the load 12.
The system stabilizing device 20 has a self-contained control unit 21, an interconnected control unit 22, a change-over switch 23, a current control unit 24, a PWM (pulse width modulation) modulator 25, a power converter 26 capable of an inverting action and a converting or rectifying action, and a direct current charging unit 27 such as an electric double layer capacitor or a battery.
The power converter 26 acts responsive to a gate signal g fed from the PWM modulator 25. This power converter 26, when performing a converting action, converts an alternating current power obtained from the distribution system 10 into a direct current power, and charges this direct current power into the direct current charging unit 27. When performing an inverting action, the power converter 26 converts the direct current power charged in the direct current charging unit 27 into an alternating current power, and sends this alternating current power to the distribution system 10.
In the system stabilizing device 20, moreover, a system current Is, which flows from the power system 1 into the distribution system 10, is detected by a current detector 28, a system voltage Vs which is the voltage of the distribution system 10 is detected by a voltage detector 29, and a converter current Iinv inputted to and outputted from the power converter 26 is detected by a current detector 30.
With the system stabilizing device 20, under normal conditions where no breakdown or the like occurs in the power system 1, the circuit breaker 2 is in a connected state, so that “a system-interconnected run”, an operation performed with the distribution system 10 being tied to the power system 1, is carried out. During the system-interconnected run, electric power is supplied to the load 12 by the power system 1, the dispersed generation plant 11, and the system stabilizing device 20.
During this system-interconnected run, a movable contact 23a of the change-over switch 23 is thrown to the A side as indicated by a dashed line in FIG. 7. As a result, the gate signal g obtained under control of the interconnected control unit 22 is fed to the power converter 26 to actuate the power converter 26.
During the above system-interconnected run, the system stabilizing device 20 acts to detect the system current Is flowing into the distribution system 10, determine a system power from the system current Is, and suppress a fluctuation in this system power. That is, the system stabilizing device 20 acts to detect a power flow at the point of interconnection between the distribution system (microgrid) 10 and the power system 1 and render fluctuations in the power flow gentle.
Under abnormal conditions where a breakdown occurs in the power system 1, on the other hand, the circuit breaker 2 is in a shut-off state, and the system stabilizing device 20 makes a “self-supporting run”, a run performed with the distribution system 10 being cut off from the power system 1. During the self-supporting run, electric power is supplied to the load 12 by the dispersed generation plant 11 and the system stabilizing device 20.
During this self-supporting run, the movable contact 23a of the change-over switch 23 is thrown to the B side as indicated by a solid line in FIG. 7. As a result, the gate signal g obtained under control of the self-contained control unit 21 is fed to the power converter 26 to actuate the power converter 26.
During the above self-supporting run, the system stabilizing device 20 detects the system voltage Vs within the distribution system 10, and performs a compensating action so that the voltage amplitude and frequency of this system voltage Vs become stable. That is, the system stabilizing device 20 detects an excess or deficiency in the power within the distribution system (microgrid) 10, and exercises input or output control over the power such that surplus power is charged into the direct current charging unit 27 when the power within the microgrid 10 is greater than the load power, and the charged power is outputted when the load power is insufficient.
Details of the actions of the system stabilizing device 20 during the self-supporting run will be described by reference to FIG. 8.
During the self-supporting run, power is supplied from the dispersed generation plant 11 to the load 12. When the power load sharply increases at this time, the torque of the generator becomes insufficient for the load power, so that the number of revolutions decreases to lower the frequency of the voltage.
Governor control for maintaining the frequency of the output voltage at a constant value is applied to the internal combustion engine type power generation equipment. However, governor control is slow in response, so that if the load sharply increases, a decrease in the frequency lasting for several seconds or so occurs. As noted here, a load change (sharp increase in load) causes a great change to the frequency. According to this change, other power generation equipment within the microgrid 10 also increases in load, and governor control is performed for the other power generation equipment as well. It follows that governor control is exercised in a plurality of power generation equipment. If such a plurality of governor controls interfere with each other, oscillations, etc. occur in the system voltage, rendering power supply from the dispersed generation plant 11 to the load 12 unstable.
Under this situation, upon detection of a decrease in the frequency of the system voltage Vs, the system stabilizing device 20 outputs an active power to assist governor control of the internal combustion engine type power generation equipment, keeping a decrease in frequency to a minimum.
During the self-supporting run, moreover, power is supplied from the dispersed generation plant 11 to the load 12. When the load increases, a voltage drop in the system voltage Vs is caused by an armature reaction due to armature inductance LG within the generator of the power generation equipment.
AVR (automatic voltage regulating) control for maintaining the output voltage at a constant value is applied to the internal combustion engine type power generation equipment. However, AVR control is slow in response, so that if the load sharply increases, a decrease in the voltage lasting for several seconds or so occurs. As noted here, a load change or fluctuation causes a great change to the voltage.
Under this situation, upon detection of a voltage drop in the system voltage Vs, the system stabilizing device 20 outputs a reactive power, thus acting as a capacitor load, to cancel out the voltage drop in the armature inductance LG, thereby suppressing the voltage drop in the system voltage Vs.
By performing the above-mentioned two types of actions, the system stabilizing device 20 suppresses fluctuations in the frequency and amplitude (voltage value) of the system voltage Vs to improve power quality.
By further reference to FIG. 8, explanations will be offered for the configurations and actions of respective functional blocks which act during the self-supporting run among the respective functional blocks of the system stabilizing device 20.
A zero-crossing detecting unit 40 takes in the system voltage Vs detected by the voltage detector 29, and outputs a zero-crossing signal Z showing the interval between the zero-crossings of its sinusoidal waveform. A frequency converting unit 41 outputs a frequency signal ωs showing the frequency of the system voltage Vs based on the zero-crossing signal Z.
A fluctuation detecting block 42 determines the fluctuation component Cωs of the frequency signal ωs, and this fluctuation component Cωs is integrated by an integrator 43 to determine an active current command Irefd.
A voltage amplitude detecting unit 44 takes in the system voltage Vs detected by the voltage detector 29, and outputs a voltage amplitude signal |Vs| showing its voltage value.
A fluctuation detecting block 45 determines the fluctuation component C|Vs| of the voltage amplitude signal |Vs|, and this fluctuation component C|Vs| is multiplied by a predetermined gain by a proportional computing unit 46 to determine a reactive current command Irefq.
A PLL (phase-locked loop) circuit 50 is composed of a PLL computing unit 51, an adder 52, and an integrator 53.
This PLL circuit 50 outputs a control reference phase θ. The PLL computing unit 51 receives the zero-crossing signal Z and the control reference phase θ, and outputs a frequency difference Δωs. The adder 52 adds the frequency difference Δωs and a reference angular frequency ωs*, and the resulting sum Δωs+ωs) is integrated by the integrator 53 to output the control reference phase θ.
With this control reference phase θ as a phase reference, the transforming actions of a dq transformer 60 and a dq inverse transformer 65 to be described later are performed.
The dq transformer 60 carries out dq transformation of the converter current Iinv detected by the current detector 30 to output the active component Iinvd of the converter current and the reactive component Iinvq of the converter current.
A subtracter 61 outputs the active component Δd of a current deviation which is a deviation between the active current command Irefd and the active component Iinvd of the converter current. A current control unit (ACR) 62 performs the PI (proportional plus integral) computation of the active component Δd of the current deviation to output an active voltage command Vd.
A subtracter 63 outputs the reactive component Δq of a current deviation which is a deviation between the reactive current command Irefq and the reactive component Iinvq of the converter current. A current control unit (ACR) 64 performs the PI (proportional plus integral) computation of the reactive component Δq of the current deviation to output a reactive voltage command Vq.
The dq inverse transformer 65 carries out the dq inverse transformation of the active voltage command Vd and the reactive voltage command Vq to output a voltage command V*.
The PWM (pulse width modulation) modulator 25 PWM-modulates the voltage command V* to produce the gate signal g, and the power converter 26 acts in response to this gate signal g.
As a result, when the frequency signal ωs declines, power compensation is made such that active power is outputted from the power converter 26, or when the voltage amplitude signal |Vs| declines, power compensation is made such that reactive power is outputted from the power converter 26.
A fluctuation detecting block 70 and a fluctuation detecting block 80, which can be used as the fluctuation detecting blocks 42, 45 (see FIG. 8), will be described by reference to FIGS. 9 and 10.
The fluctuation detecting block 70 shown in FIG. 9 can be used as the fluctuation detecting blocks 42, 45 (see FIG. 8).
The fluctuation detecting block 70 is composed of a low-pass filter 71, a low-pass filter 72, a subtracter 73, an amplifier 74, and a rating limiter 75.
The pass band frequency of the fluctuation detecting block 70 is determined by filtering characteristics required of the fluctuation detecting block 42 or the fluctuation detection block 45.
The low-pass filter 71 is a filter having first order lag characteristics, whose time constant is set to be the time constant T1. The time constant T1 is a time constant which has been determined for the purpose of noise removal.
The low-pass filter 72 is a filter having first order lag characteristics, whose time constant is set to be the time constant T2. The time constant T2 is a time constant which has been determined for the purpose of setting the time for detecting fluctuations.
When receiving an input signal (frequency signal ωs or voltage amplitude signal |Vs|), both filters 71 and 72 utilize their filtering characteristics to filter the input signal.
The subtracter 73 outputs a fluctuation component obtained by subtracting an output signal of the low-pass filter 72 from an output signal of the low-pass filter 71.
The fluctuation component outputted from the subtracter 73 is amplified by the amplifier 74. That is, −G as a negative gain has been set in the amplifier 74, and the fluctuation component is multiplied by −G.
Further, the fluctuation component amplified by the amplifier 74 is outputted after passage through the rating limiter 75. Thus, the upper limit value and lower limit value of its signal value (command value) are limited to the rated value, and then outputted.
The active current command Irefd and the reactive current command Irefq are determined based on the signals (fluctuation components Cω, C|Vs|) outputted from the rating limiter 75 (see FIG. 8).
That is, when the fluctuation detecting block 70 is used as the fluctuation detecting block 42, the active current command Irefd is determined by integrating the signal (fluctuation component Cωs) outputted from the rating limiter 75. When the fluctuation detecting block 70 is used as the fluctuation detecting block 45, the reactive current command Irefq is determined by multiplying the signal (fluctuation component C|Vs|) outputted from the rating limiter 75 by a predetermined gain.
The fluctuation detecting block 80 shown in FIG. 10 can be used as the fluctuation detecting blocks 42, 45 (see FIG. 8).
The fluctuation detecting block 80 is composed of a low-pass filter 81, a limiter 82, a delay circuit 83, a first subtracter 84, a second subtracter 85, an adder 86, an amplifier 87, and a rating limiter 88.
The pass band frequency of the fluctuation detecting block 80 is determined by filtering characteristics required of the fluctuation detecting block 42 or the fluctuation detecting block 45.
The low-pass filter 81 is a filter having first order lag characteristics, whose time constant is set to be the time constant T1. The time constant T1 is a time constant which has been determined for the purpose of noise removal.
When receiving an input signal (frequency signal ωs or voltage amplitude signal |Vs|), the low-pass filter 81 utilizes its filtering characteristics to filter the input signal.
The limiter 82 has limiting characteristics defined as ±(X/T3)Ts.
T3 represents a cushioning time set at an arbitrary duration, Ts represents one sampling period, and X represents a limiting value.
This limiter 82 limits the amount of change for one sampling period Ts. When the signal value of the signal inputted to the limiter 82 is a value between +X (upper limiting value) and −X (lower limiting value), the limiter 82 holds the signal value of the input signal as such, and outputs it. When the signal value of the signal inputted to the limiter 82 is above +X (upper limiting value), the limiter 82 allows the value to increase with a constant gradient for a predetermined time, and then limits the value to +X . When the signal value of the signal inputted to the limiter 82 is below −X (lower limiting value), the limiter 82 allows the value to decrease with a constant gradient for a predetermined time, and then limits the value to −X.
The delay circuit 83 has the properties of delaying the inputted signal by one sampling period Ts and outputting the delayed signal. This delay circuit 83 can be constructed, for example, by a Z transformation circuit having such properties as to show Z−1.
The subtracter 84 performs subtraction between the output signal of the filter 81 having the first order lag characteristics and the output signal of the delay circuit 83, and sends the resulting difference signal to the limiter 82.
That is, the output signal of the delay circuit 83 is provided as negative feedback at the stage preceding the limiter 82.
The adder 86 adds the signal outputted from the limiter 82 and the signal outputted from the delay circuit 83, and outputs the sum.
That is, the output signal of the delay circuit 83 is provided as positive feedback at the stage succeeding the limiter 82.
The delay circuit 83 delays the output signal of the adder 86 by one sampling period Ts, and outputs the delayed signal.
As described above, the signal outputted from the delay circuit 83 is provided as negative feedback at the stage preceding the limiter 82, and is provided as positive feedback at the stage succeeding the limiter 83. Thus, the signal status is as follows:
The output of the subtracter 84 is “the present sampled value−the value after limiter processing performed one sampling period previously”.
Thus, if the signal value inputted from the filter 81 to the subtracter 84 is +X or less, but −X or more, the signal value outputted from the limiter 82 is 0.
If the signal value inputted from the filter 81 to the subtracter 84 is above +X, but below −X, on the other hand, the signal value outputted from the limiter 82 is a value whose upper limit value and lower limit value are restricted by the limiting values (+X, −X).
The output of the adder 86 is “the output of the limiter+the value after limiter processing performed one sampling period previously”.
Thus, if the signal value inputted from the filter 81 to the subtracter 84 is above +X, but below −X, the signal value outputted from the adder 86 linearly increases. That is, the value of the signal outputted from the adder 86 varies (increases or decreases) stepwise by the magnitude of the limiting value (+X or −X) for each sampling period Ts.
The subtracter 85 performs subtraction between the output signal of the low-pass filter 81 having the first order lag characteristics and the output signal of the adder 86, and outputs the difference. A fluctuation component included in the input signal is outputted from the subtracter 85.
The fluctuation component outputted from the subtracter 85 is amplified by the amplifier 87. That is, −G as a negative gain has been set in the amplifier 87, and the fluctuation component is multiplied by −G.
Further, the fluctuation component amplified by the amplifier 87 is outputted after passage through the rating limiter 88. Thus, the upper limit value and lower limit value of its signal value (command value) are limited to the rated value, and then outputted.
The active current command Irefd and the reactive current command Irefq are determined based on the signals (fluctuation components Cωs, C|Vs|) outputted from the rating limiter 88 (see FIG. 8).
That is, when the fluctuation detecting block 80 is used as the fluctuation detecting block 42, the active current command Irefd is determined by integrating the signal (fluctuation component Cωs) outputted from the rating limiter 88. When the fluctuation detecting block 80 is used as the fluctuation detecting block 45, the reactive current command Irefq is determined by multiplying the signal (fluctuation component C|Vs|) outputted from the rating limiter 88 by a predetermined gain.